1. Field of the Invention
An aspect of the present invention relates to a semiconductor apparatus and a method for manufacturing the semiconductor apparatus, and more particularly to a semiconductor apparatus having a feature in a hard mask structure for forming a minute FeRAM capacitor structure and a method for manufacturing the semiconductor apparatus.
2. Description of the Related Art
With the advancement of the integration of ferroelectric memories (FeRAMs), it has become indispensable to form ferroelectric capacitors by performing Single-Mask Photo-Engraving Process (PEP) (hereunder sometimes referred to as a “1-Mask-1-PEP”) to perform a collective patterning processing through a reactive ion etching (RIE) method. However, in such a ferroelectric capacitor (hereunder sometimes referred to as a “1-Mask-FeRAM”), a volatility of a ferroelectric capacitor material, particularly, a volatility of an electrode material formed by a noble metal such as platinum (Pt) or iridium (Ir) is remarkably poor and hard to etch. Additionally, in an etching of the ferroelectric capacitor material using a hard mask, the side wall portion is etched more greatly than the center portion. That is, a dropped portion (shoulder drop) on an upper sidewall portion (shoulder portion) of the hard mask is easily generated. Therefore, to form a 1-Mask FeRAM by the collective patterning processing through a reactive ion etching (RIE) method, the thick hard mask is required by taking into account the poor volatility of the electrode material and the an uniformity of the etching speed of the hard mask.
To process such the thick hard mask, the thick resist mask is also required. Therefore, a miniaturization of an FeRAM is prevented.
There have been disclosed a dielectric capacitor exhibiting an excellent electrical characteristic by preventing an entrance and diffusion of an external substance such as a reducing element for a dielectric film and a method for manufacturing the dielectric capacitor (for example, see JP-A-2002-353414 and U.S. Pat. No. 6,440,815).
The JP-A-2002-353414 and U.S. Pat. No. 6,440,815 disclose a method for manufacturing a dielectric capacitor in which a resist film is used as a mask to etch an oxide film and a first hydrogen diffusion preventing film, thereby forming an oxide film as a functional film, and the oxide film is used as an etching mask for forming a ferroelectric capacitor at a sequent step and the oxide film is used as a hard mask to process a ferroelectric film, a lower electrode and a contact film by a dry etching method.